From Lev.Uvarov@cern.ch Mon May 24 15:44:59 2004
Subject: DT Interface Test results

Hi Darin,

please find picture of the DT Interface test setup at
http://www.phys.ufl.edu/~uvarov/CERN/

1. Hardware.
There are only two slots in the TF crate assembled with the DT output/input
backplane connectors: slot 9 and slot 20. The picture shows the Transition
Board sitting in slot 9. The interconnect for a loopback test is show at
http://www.phys.ufl.edu/~uvarov/CERN/LU-SP02_TB2_Setup.pdf. The SP02 DT
output signals pass through the LVTTL->LVDS level translators on the
transition board and feed the test board inputs. The test board output
signals pass through the LVDS->LVTTL level translators on the transition
board and feed the SP02 DT inputs. Two tests are required to verify the DT
output/input connections on the SP02, one for the F1_FPGA outputs and
another for the F2_FPGA outputs.
Problems:
- the TB tends to fall out, since there is no back cage installed. The
screwdriver box as a prop helps to keep the board in place.
- the SCSI cables tend to unplug and fall out, since the cable connectors
are of a wrong type: with screws instead of latches.

2. Firmware.
The Front FPGA firmware provides access from the test fifo for each DT
output signal line. The SP FPGA spy fifo has access for each DT input signal
line. Since the number of data (non-clock) DT inputs is 50, and the number
of data (non-clock) outputs for a front FPGA is 51, one data output maps to
a clock input. There is a configuration register in the SP FPGA, which
provides treating a clock input line as a data line.

3. Software
The test code provides two options:
- single run, when the front FPGA test fifo injects a "walking one" test
pattern into the data path , the SP FPGA spy fifo catches 32 bx of "DT" data
and the code dumps the spy fifo contents into a file.
- continious run, when the code cycles over the "inject test pattern"
command to provide synchronization to a scope. The injection period is about
16 us.

4. Results.
The log files for F1 and F2 loopback tests are at
http://www.phys.ufl.edu/~uvarov/CERN/
Only one problem has been encountered during the tests: the me1f_phi0 bit
does not come out from the transition board, see line 47 of the log file for
F2. We have not yet had a change to trace the missing bit further into the
backplane connector and the proper SP02.
The data comes 2-6 ns later the rising edge of the clock. This can be
adjusted if the DT guys would like to see this shift larger.

5. Plans.
If time allows we will repeat tests with the second SP (#3) that just came
in.

Regards,
            Lev, Victor, Bobby

p.s. Note added from Victor on Tuesday:

The dead line is due to one broken pin of the
in/ out connector we have found on the Backplane slot 9.
It is a pity we couldn't install the Transition Board in slot
20 due to ribbon cable is located just over the in/ out
connector.