VME-JTAG interface

Updated 4/17/2003

 

This interface is designed mostly for downloading the configuration into the on-board FPGAs and EEPROMs via JTAG interface, which is now an industry-standard approach.

 

The main idea is to have a very simple VME glue logic on the board, which allows the control software to access SCANPSC100F - an 8-bit parallel bus to JTAG converter made by National. See specs here:

 

http://www.national.com/ds/SC/SCANPSC100F.pdf

 

The glue logic is implemented in a small Xilinx CPLD. It has to be programmed only once for the lifetime of the board.

 

This approach allows to program all FPGAs and EEPROMs on the boards, including the VME interface FPGA, since the JTAG glue logic is located in a separate CPLD.

 

Interface schematics can be found here:

 

JTAG_INTERFACE - JINT.pdf

 

On this schematics:

U137 – SCANPSC100F – parallel JTAG interface

U120 – XC9572XL-7TQ100C – glue logic CPLD

 

The glue logic CPLD provides also the JTAG chain multiplexer for 3 chains (see notes at the bottom of the schematics).

 

CPLD Verilog HDL code is here:

 

Main file: sp02_jtag_cpld.v

Submodule: sp_jtag_cpld.v  

 

National provides a free software package to operate SCANPSC100F, which was adapted by the authors to work via VME using SBS BIT3 620 controller. It can be easily modified to use any other VME controller. It takes the files in EVF format and downloads them via JTAG into any FPGA, EPROM or CPLD. Multiple devices can be linked into one JTAG chain. This particular version of the software was compiled with GNU C++ compiler on Linux 7.2, but using it on other platforms, such as Microsoft Windows, is also possible.

 

bedtest_07.24.03.tgz

 

To use bedtest software, do this:

  1. Generate SVF file using Xilinx ISE software, or any other software supporting SVF format. We have verified it with multiple versions of Xilinx ISE, up to version 5.1 SP3.
  2. Convert SVF file into EVF format using this Windows routine:  svf3evf.exe
  3. Load the file into the board:

 

bedtest file.evf slot chain

 

·        file.evf is the name of the file generated in step 2

·        slot is a slot number in VME crate where the board is located (2..21). Bedtest converts slot number into base address using this formula:

baseaddr = (slot&0x1f) << 19;

·        chain is a JTAG chain number (0..2), programmable via glue logic (see CPLD code above).

 

Example:
bedtest configuration.evf 14 1 will load “configuration.evf “ file into the board in slot 14, selecting JTAG chain 1.

 

 

Free JAM software provided by Altera was adapted to work via this interface, so Altera’s devices can also be programmed. Let me know if you want it.