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Pixel 00 R
&D
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Occupancy, bandwidth, and trigger latency
study for a CDF pixel replacement of Layer 00 for Run IIb.
Examines whether a BTeV style periphery for the FPIX chip could work for CDF II.
PIX00 Monte-Carlo Simulations:
These plots are not correct!
Preliminary PIX00 Occupancy Studies
(9 pages: Adobe Acrobat PDF file)
These plots are not correct!
More Preliminary PIX00 Occupancy Studies
, talk presented by R. Field on October 5, 2000
(12 pages: Adobe Acrobat PDF file).
New Correct PIX00 Occupancy Studies
, 10,000 Top plus <3> Min-Bias at 2 TeV, 250 micron thick pixels, bug fixed!
(6 pages: Adobe Acrobat PDF file).
Chip with Maximum Hits,
one plot: 10,000 Top plus <3> Min-Bias at 2 TeV, 250 micron thick pixels, chip = 2,880 pixels, bug fixed!
(EPS file).
More PIX00 Plots,
10,000 Top plus <3> Min-Bias at 2 TeV, 250 micron thick pixels, bug fixed, includes "track lengths", position of "hot" chips,
and some sigmaz = 0 comparisons
(12 pages: Adobe Acrobat PDF file).
More PIX00 Plots,
10,000 <3> Min-Bias (no top) at 2 TeV, 250 micron thick pixels, sigmaz = 30 cm, bug fixed
(9 pages: Adobe Acrobat PDF file).
More PIX00 Plots,
10,000 Top plus <3> Min-Bias at 2 TeV, 250 micron thick pixels, sigmaz = 30 cm, bug fixed, Half-Module-Ring Information
(3 pages: Adobe Acrobat PDF file).
A Few Events:
- Event 35: Top + 7 Min-Bias at 2 TeV (chip with max hits = 42 hits, 270 micron thick pixels)
- Event 64: Top + 1 Min-Bias at 2 TeV (chip with max hits = 36 hits, 270 micron thick pixels)
Send
comments and suggestions to rfield@phys.ufl.edu
Rick Field - Last modified: February 2, 2001