Sector Processor (SP05) Design

 

This is a complementary page to the CSC Track-Finder main page.

It provides details on the CSC Sector Processor design.

Updates are cumulative: later updates (unless specifically noted) include previous updates

 

Sector Processor Schematics, pre-production version (2004)

Sector Processor Schematics, production version (2005)

SP Mezzanine Card Schematics (SP core FPGA)

SP Daughter Board Schematics (QPLL board)

SP Transition Board Schematics (CSC ó DT interface)

DDU Extender Board Schematics (for DDU in the TF crate)

VME_CPLD configuration (Jul 28, 2008 version)

 

Firmware Under Test:

Jun 01, 2009
(ISE 9.2i)

MC08/SP: with new core dated Mar 26, 2009;

SP svf file for chain0 and chain0 XCF08P mcs files
CNT_ETA, DAT_ETA, CSR_SCC Register Update

 

Latest Firmware Updates:

May 21, 2009
(ISE 9.2i)

FA, DD, VM: “double resynch” and “FMM reporting” bug fix version

SP svf file for chain1 and chain1 XC18V04 mcs files

 

Mar 14, 2009
(ISE 9.2i)

SP: Singles’ PHI [4:0] scale now matches Tracks’ PHI [4:0] scale in SP Data Record;

SP svf file for chain0_xc5v and chain0 XCF08P mcs files

 

Oct 15, 2008
(ISE 9.2i)

FA: 081015 version: fixed a “link fails to Resync” problem;
FA: added D[12] = “signal detect of FINISAR optical receiver” bit to the CSR_AF register => this is a copy of CSR_LNK/D[8] bit => now all link diagnostic is in one register
VM, DD: 080801 version

SP svf file for chain1 and fa XC18V04 mcs files

 

Sep 10, 2008
(ISE 9.2i)

SP: added delay (0…3) for beam halo triggers in CSR_SCC/MA/SP/D[13:12];
SP: added delay (0…7) for CSC stubs in CSR_AFD/MA/SP/D[6:4]; and mcs file

SP svf file for chain0 and chain0 XC18V04 mcs files

SP svf file for chain0_xc5v  and  SP_FPGA bit file and chain0 XCF32 mcs files

 

Aug 08, 2008
(ISE 9.2i)
for CRUZET-4:

Bug-fix version

SP svf file for chain0 and chain0 XC18V04 mcs files

SP svf file for chain1 and chain1 XC18V04 mcs files

 

May 14, 2008
(ISE 9.2i)
for CRUZET-3:

(FA: added LCT Quality Enable or CSR_LQE register; modified CSR_OSY to better monitor MPC-to-SP links;
DD: added BC0 Delay or CSR_BCD register;
SP: eliminated DAT_FTR, assigned Mode=11=0xB for triggers on single stubs, assigned stub’s MEn_ID/MB_ID, ETA and PHI for such pseudo tracks; assigned Halo=1 for Mode=15=0xF; CSR_SCC modified to mask Q=1 and Q=2, instead of Q=3 and Q=4)

SP1 svf file for chain0 (core version #1; + 4 bx latency compared to core version #0)

SP svf file for chain1 (Asynchronous FIFO core v5.1; min latency 2.X clock cycles)

SP svf file for chain1 (FIFO Generator, v4.2; min latency 6.X clock cycles)

CSR_AF, CSR_SCC, CSR_LQE, CSR_OSY, ACT_LCR, CSR_BCD Register Update v3

TF Monitorables for CRUZET 2 Update

SP Readout Format to v5.2B Update

 

Apr 08, 2008
(ISE 9.2i)
for CRUZET:

(All chips: complete ISE9.2i release with extended idtb timing => recommended for installation in USC)

SP1 svf file for chain0 (core version #1; + 5 bx latency compared to core version #0)

SP0 svf file for chain0 (core version #0)

SP svf file for chain1

CSR_SCC and  DAT_ETA Register Update

TF Monitorables for CRUZET

 

Jan 28, 2008
(ISE 5.2i):

(FA: updated MPC link control and monitoring for out-of-sync occurences)

SP05 svf file for chain1

FA: CSR_OSY and ACT_LCR Register Update

 

Dec 06, 2007
(ISE 5.2i):

(DD: updated SP_ERSV to 2)

SP05 svf file for chain1

SP05 Readout Format v5.2A

 

Oct 25, 2007
(ISE 5.2i):

(DD: Readout Format updated to 5.2 and CSR_BID modified;
VM: LUT monitoring/verification logic implemented;
SP: L1REQ on singles modified;
All chips: ME1 timed-in earlier, than ME2/ME3/ME4 by an offset to minimize latency to DTTF)

SP05 svf file for chain0

SP05 svf file for chain1

SP LUT Downloading and Verification Procedure

SP05 Readout Format v5.2

Updated VM/ACT_XFR, SP/CSR_AFD , DD/CSR_BID and SP/CSR_REQ Registers,
Added ACT_LUT, CSR_MF, DAT_MF, CSR_VF, and DAT_VF Registers

 

Jul 06, 2007
(ISE 5.2i):

(DD: CSR_BID modified;
SP: Readout Format updated to 5.1; SP core latency increased by 2bx for ME stubs to match MB stub latency; MB input timing re-adjusted)

SP05 svf file for chain0

SP05 svf file for chain1

SP05 Readout Format v5.1

CSR_BID and ACT_LCR Register Update

 

Jun 21, 2007
(ISE 5.2i):

(All chips: CCB Interface Update: Start Data Taking, Stop Data Taking control eliminated, SP is Free Running)

SP05 svf file for chain0

SP05 svf file for chain1

CCB Interface Update

 

May 28, 2007
(ISE 5.2i):

(SP: DAT_FTR to fake PT LUT output on single VP added)

SP05 svf file for chain0

SP/MA/DAT_FTR Register

 

Mar 22, 2007
(ISE 5.2i):

(VM: CSR_FMM control added;
FA: same as of Aug 01, 2006;
DD: same as of Jan 09, 2007)

SP05 svf file for chain1

VM/MA/CSR_FMM Register

 

Jan 09, 2007
(ISE 5.2i):

(VM, FA: same as of Aug, 1,
DD: data coded LSB first, CRC reversed bit order)

SP05 svf file for chain1

 

Aug 1, 2006
(ISE 5.2i):

(VM: added CSR_REQ to delay L1req;
DD: inserted 4 idles between events;
FA, SP: fixed DT quality bits mapping)

SP05 svf file for chain0

SP05 svf file for chain1

VM/MA/CSR_REQ Register

 

Jul 1, 2006
(ISE 5.2i):

(VM, FA, DD, SP: readjusted FC_CMD timing,
SP: added delay for CSC stubs in SP_FPGA)

SP05 svf file for chain0

SP05 svf file for chain1

SP05 Registers

SP05 Readout Format v4.2

 

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Last modified June 5, 2009 by Lev Uvarov