Sector Processor (SP05) Design
This is a complementary page to the CSC Track-Finder main page.
It provides details on the CSC Sector Processor design.
Updates are cumulative: later updates (unless specifically noted) include previous updates
Sector Processor Schematics, pre-production version (2004)
Sector Processor Schematics, production version (2005)
SP Mezzanine Card Schematics (SP core FPGA)
SP Daughter Board Schematics (QPLL board)
SP Transition Board Schematics (CSC ó DT interface)
DDU Extender Board Schematics (for DDU in the TF crate)
Latest Firmware Updates:
May 14, 2008:	(FA: added LCT Quality Enable or CSR_LQE register; modified CSR_OSY to better monitor MPC-to-SP links; DD: added BC0 Delay or CSR_BCD register; SP: eliminated DAT_FTR, assigned Mode=11=0xB for triggers on single stubs, assigned stub’s MEn_ID/MB_ID, ETA and PHI for such pseudo tracks; assigned Halo=1 for Mode=15=0xF; CSR_SCC modified to mask Q=1 and Q=2, instead of Q=3 and Q=4)
ISE 9.2i	SP1 svf file for chain0 (core version #1; + 4 bx latency compared to core version #0)
ISE 9.2i	SP svf file for chain1 (Asynchronous FIFO core v5.1; min latency 2.X clock cycles)
ISE 9.2i	SP svf file for chain1 (FIFO Generator, v4.2; min latency 6.X clock cycles)
For CRUZET-3	CSR_AF, CSR_SCC, CSR_LQE, CSR_OSY, ACT_LCR, CSR_BCD Register Update v3
	TF Monitorables for CRUZET 2 Update
	SP Readout Format to v5.2B Update
Apr 08, 2008:	(All chips: complete ISE9.2i release with extended idtb timing => recommended for installation in USC)
ISE 9.2i	SP1 svf file for chain0 (core version #1; + 5 bx latency compared to core version #0)
ISE 9.2i	SP0 svf file for chain0 (core version #0)
ISE 9.2i	SP svf file for chain1
For CRUZET	CSR_SCC and DAT_ETA Register Update
	TF Monitorables for CRUZET
Jan 28, 2008:	(FA: updated MPC link control and monitoring for out-of-sync occurences)
ISE 5.2i	SP05 svf file for chain1
	FA: CSR_OSY and ACT_LCR Register Update
Dec 06, 2007:	(DD: updated SP_ERSV to 2)
ISE 5.2i	SP05 svf file for chain1
	SP05 Readout Format v5.2A
Oct 25, 2007:	(DD: Readout Format updated to 5.2 and CSR_BID modified; VM: LUT monitoring/verification logic implemented; SP: L1REQ on singles modified; All chips: ME1 timed-in earlier, than ME2/ME3/ME4 by an offset to minimize latency to DTTF)
ISE 5.2i	SP05 svf file for chain0
ISE 5.2i	SP05 svf file for chain1
	SP LUT Downloading and Verification Procedure
	SP05 Readout Format v5.2
	Updated VM/ACT_XFR, SP/CSR_AFD , DD/CSR_BID and SP/CSR_REQ Registers, Added ACT_LUT, CSR_MF, DAT_MF, CSR_VF, and DAT_VF Registers
Jul 06, 2007:	(DD: CSR_BID modified; SP: Readout Format updated to 5.1; SP core latency increased by 2bx for ME stubs to match MB stub latency; MB input timing re-adjusted)
ISE 5.2i	SP05 svf file for chain0
ISE 5.2i	SP05 svf file for chain1
	SP05 Readout Format v5.1
	CSR_BID and ACT_LCR Register Update
Jun 21, 2007:	(All chips: CCB Interface Update: Start Data Taking, Stop Data Taking control eliminated, SP is Free Running)
ISE 5.2i	SP05 svf file for chain0
ISE 5.2i	SP05 svf file for chain1
	CCB Interface Update
May 28, 2007:	(SP: DAT_FTR to fake PT LUT output on single VP added)
ISE 5.2i	SP05 svf file for chain0
	SP/MA/DAT_FTR Register
Mar 22, 2007:	(VM: CSR_FMM control added; FA: same as of Aug 01, 2006; DD: same as of Jan 09, 2007)
ISE 5.2i	SP05 svf file for chain1
	VM/MA/CSR_FMM Register
Jan 09, 2007:	(VM, FA: same as of Aug, 1, DD: data coded LSB first, CRC reversed bit order)
ISE 5.2i	SP05 svf file for chain1
Aug 1, 2006:	(VM: added CSR_REQ to delay L1req; DD: inserted 4 idles between events; FA, SP: fixed DT quality bits mapping)
ISE 5.2i	SP05 svf file for chain0
ISE 5.2i	SP05 svf file for chain1
	VM/MA/CSR_REQ Register
Jul 1, 2006:	(VM, FA, DD, SP: readjusted FC_CMD timing, SP: added delay for CSC stubs in SP_FPGA)
ISE 5.2i	SP05 svf file for chain0
ISE 5.2i	SP05 svf file for chain1
	SP05 Registers
	SP05 Readout Format v4.2
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Last modified June 25, 2008 by Lev Uvarov